The invention relates to arrangements for maintaining out-of-order queue cache coherency and for prevention of memory write starvation.
In order to achieve computing systems with greater versatility and speeds, systems have been derived (see FIG. 1, e.g., described ahead) where there are a plurality of processors each having a cache associated therewith. In addition, there may be one or more integrated circuits (ICs) interfacing with, and controlling access to, main system memory. Such computing systems may support out-of-order handling of memory requests. When such computing systems have a plurality of processings ongoing at any given time, with multiple xe2x80x9ccachedxe2x80x9d copies of memory portions co-existing throughout the system at any given time and with a plurality of processors and other devices competing for memory accesses, at least two problems can arise, i.e., memory incoherency and memory write starvation. Both problems can result in erroneous system operation.
Regarding incoherency, if multiple sources within the system store incoherent (e.g., unmatched) data having differing values, any number of erroneous operations can occur. For example, a copy of an updated and correct memory portion existing somewhere within the system, has the danger of being erroneously overwritten or superceded by older, outdated and erroneous memory portion. In addition, if multiple sources attempt to respond to a memory read request and simultaneously output incoherent copies of a memory portion, a clash may occur when the multiple sources simultaneously attempt to drive differing values onto a common data bus. Data corruption and/or system error/lockup are distinct possibilities.
Regarding memory write starvation, conditions may exist where a memory write necessary for subsequent computing operations is never able to be written to memory, and thus the system may enter an endless loop situation.